Innovative Nanocomposites for Low Power Phase?Change Memory: GeTe/C Multilayers

Low Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)

Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...

Counter / Generators for Low Power Memory BIST

In today’s Integrated Circuits (IC’s) designs Built-in Self Test (BIST) is becoming important for the memory which is the most necessary part of the System on Chip. The March algorithm has been widely used to test memory core of System on chip (SOC). LFSRs and counters are mainly used to generate the memory addresses, which can be serially applied to the memory cores under test. In this paper A...

Conforming block inversion for low power memory

In this paper, we propose a scheme for reducing the power consumption of memory components by conforming memory contents to a precharging value. The scheme is oriented to application to single bitline structure of memory. It selectively stores normal or inverted data to reduce the number of bit accesses that have different values from the precharging value, which reduces overall bitline togglin...

Tapping ZettaRAMTM for Low-Power Memory Systems

ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor in each DRAM cell with “charge-storage” molecules – a molecular capacitor. We look beyond ZettaRAM’s manufacturing benefits, and approach it from an architectural viewpoint to discover benefits within the domain of ar...

Magnetic hardening in SmCox–Co multilayers and nanocomposites